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PCM4104
SBAS291B - AUGUST 2003 - REVISED MARCH 2004
High Performance, 24 Bit, 200kHz Sampling, Four Channel Audio Digital to Analog Converter
FEATURES D Four High-Performance, Multi-Level, D Differential Voltage Outputs
Delta-Sigma Digital-to-Analog Converters - Full-Scale Output (Differential): 6.15VPP
D Supports Sampling Frequencies up to 200kHz D Typical Dynamic Performance (24-Bit Data) D D D
- Dynamic Range (A-Weighted): 118dB - THD+N: -100dB Linear Phase, 8x Oversampling Digital Interpolation Filter Digital De-Emphasis Filters for 32kHz, 44.1kHz, and 48kHz Sampling Rates Soft Mute Function - All-Channel Mute via the MUTE Input Pin - Per-Channel Mute Available in Software Mode Digital Attenuation (Software Mode Only) - Attenuation Range: 0dB to -119.5dB - 256 Steps with 0.5dB per Step Output Phase Inversion (Software Mode Only) Zero Data Mute (Software Mode Only) Audio Serial Port - Supports Left-Justified, Right-Justified, I2SE, and TDM Data Formats - Accepts 16-, 18-, 20, and 24-Bit Two's Complement PCM Audio Data Standalone or Software-Controlled Configuration Modes Four-Wire Serial Peripheral Interface (SPIE) Port Provides Control Register Access in Software Mode Power Supplies: +5V Analog, +3.3V Digital Power Dissipation - 203mW typical with fS = 48kHz - 220mW typical with fS = 96kHz - 236mW typical with fS = 192kHz Power-Down Modes Small 48-Lead TQFP Package
APPLICATIONS D Digital Mixing Consoles D Digital Audio Workstations D Digital Audio Effects Processors D Broadcast Studio Equipment D Surround-Sound Processors D High-End A/V Receivers DESCRIPTION
The PCM4104 is a high-performance, four-channel digital-to-analog (D/A) converter designed for use in professional audio applications. The PCM4104 supports 16- to 24-bit linear PCM input data, with sampling frequencies up to 200kHz. The PCM4104 features lower power consumption than most comparable stereo audio D/A converters, making it ideal for use in high channel count applications by lowering the overall power budget required for the D/A conversion sub-system. The PCM4104 features delta-sigma architecture, employing a high-performance multi-level modulator combined with a switched capacitor output filter. This architecture yields lower out-of-band noise and a high tolerance to system clock phase jitter. Differential voltage outputs are provided for each channel and are well-suited to high-performance audio applications. The differential outputs are easily converted to a single-ended output using an external op amp IC. The PCM4104 includes a flexible audio serial port interface, which supports standard and time division multiplexed (TDM) formats. Support for TDM formats simplifies interfacing to DSP serial ports, while supporting a cascade connection for two PCM4104 devices. In addition, the PCM4104 offers two configuration modes: Standalone and Software-Controlled. The Standalone mode provides dedicated control pins for configuring a subset of the available PCM4104 functions, while Software mode utilizes a serial peripheral interface (SPI) port for accessing the complete feature set via internal control registers. The PCM4104 operates from a +5V analog power supply and a +3.3V digital power supply. The digital I/O is compatible with +3.3V logic families. The PCM4104 is available in a TQFP-48 package.
D D D D
D D D D
D D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003-2004, Texas Instruments Incorporated
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PCM4104
www.ti.com SBAS291B - AUGUST 2003 - REVISED MARCH 2004
ORDERING INFORMATION
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) PFB SPECIFIED TEMPERATURE RANGE -10C to +70C PACKAGE MARKING PCM4104PFB ORDERING NUMBER PCM4104PFBT PCM4104 TQFP-48 PCM4104PFBR (1) For the most current specification and package information, refer to our web site at www.ti.com. TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2000
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) PCM4104 Supply voltage Ground voltage difference VCC VDD Any AGND-to-AGND and AGND-to-DGND FS0, FS1, FMT0, FMT1, FMT2, CDOUT, CDIN, CCLK, CS, DATA0, DATA1, BCK, LRCK, SCKI, SUB, DEM0, DEM1, MUTE, RST, MODE +6.0 +3.6 0.1 -0.3 to (VDD + 0.3) 10 -10 to +70 UNIT V V V
Digital input voltage
V
Input current (any pin except supplies) Operating temperature range
mA C
Storage temperature range, TSTG -65 to +150 C (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
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PCM4104
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ELECTRICAL CHARACTERISTICS
All parameters are specified at TA = +25C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. PCM4104 PARAMETER
RESOLUTION DATA FORMAT Audio data formats Audio data word length Binary data format CLOCK RATES AND TIMING Single rate sampling mode System clock frequency fSCKI Dual rate sampling mode Quad rate sampling mode Single rate sampling mode Sampling frequency fS Dual rate sampling mode Quad rate sampling mode SPI port data clock SPI port data clock high time SPI port data clock low time DIGITAL INPUT/OUTPUT Input logic level VIH VIL IIH IIL VOH VOL VIN = VDD VIN = 0V IOH = -2mA IOH = +2mA 2.4 0.4 1 1 2.0 0.8 10 -10 V V A A V V fCCLK tCCLKH tCCLKL 15 15 6.144 12.8 12.8 24 50 100 36.864 36.864 36.864 50 100 200 24 MHz MHz MHz kHz kHz kHz MHz ns ns Left or Right Justified, I2S, and TDM 16 24 Bits
CONDITIONS
MIN
TYP
24
MAX
UNITS
Bits
Two's Complement Binary, MSB First
Input logic current
Output logic level ANALOG OUTPUTS Full-scale output voltage, differential Bipolar zero voltage Output impedance
RL = 600
6.15 2.5 5
VPP V Ohms dB % FSR % FSR mV V 200 A
Switched capacitor filter frequency response Gain error Gain mismatch, channel-to-channel Bipolar zero error VCOM1 and VCOM2 output voltage VCOM1 and VCOM2 output current
f = 20kHz, all sampling modes
-0.2 0.5 0.6 1
VCC = +5V
2.5
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PCM4104
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ELECTRICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. PCM4104 PARAMETER
DYNAMIC PERFORMANCE WITH 24-BIT DATA(1) fS = 48kHz f = 1kHz at 0dBFS Total harmonic distortion + noise Dynamic range, A-weighted Idle channel SNR, A-weighted Idle channel SNR, unweighted Channel separation fS = 96kHz f = 1kHz at 0dBFS, BW = 10Hz to 40kHz Total harmonic distortion + noise Dynamic range, A-weighted Idle channel SNR, A-weighted Idle channel SNR, unweighted Channel separation fs = 192kHz f = 1kHz at 0dBFS, BW = 10Hz to 40kHz Total harmonic distortion + noise Dynamic range, A-weighted Idle channel SNR, A-weighted Idle channel SNR, unweighted Channel separation THD+N f = 1kHz at -60dBFS, BW = 10Hz to 40kHz f = 1kHz at -60dBFS All zero input data All zero input data, BW = 10Hz to 40kHz f = 1kHz at 0dBFS for active channel -97 -53 118 118 113 110 dB dB dB dB dB dB THD+N f = 1kHz at -60dBFS, BW = 10Hz to 40kHz f = 1kHz at -60dBFS All zero input data All zero input data, BW = 10Hz to 40kHz f = 1kHz at 0dBFS for active channel -100 -53 118 119 113 110 dB dB dB dB dB dB THD+N f = 1kHz at -60dBFS f = 1kHz at -60dBFS All zero input data All zero input data f = 1kHz at 0dBFS for active channel 100 112 -100 -56 118 119 116 110 -94 dB dB dB dB dB dB
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE WITH 16-BIT DATA fs = 44.1kHz f = 1kHz at 0dBFS Total harmonic distortion + noise Dynamic Range, A-weighted Idle channel SNR, A-weighted(2) Idle channel SNR, unweighted(2) THD+N f = 1kHz at -60dBFS f = 1kHz at -60dBFS All zero input data All zero input data -92 -33 96 118 115 dB dB dB dB dB
(1) Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. Input data word length is 24 bits with triangular PDF dither added for dynamic range and THD+N tests. Idle channel SNR is measured with both the soft and zero data mute functions disabled and 0% full-scale input data with no dither applied. The measurement bandwidth is limited by using the Audio Precision 10Hz high-pass filter in combination with either the AES17 20kHz low-pass filter or AES17 40kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination with either the 22kHz or 80kHz low-pass filter. Measurement mode is set to RMS for all parameters. The AVERAGE measurement mode will yield better typical performance numbers. (2) Idle Channel SNR is not limited by word length.
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PCM4104
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ELECTRICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. PCM4104 PARAMETER
DIGITAL FILTERS 0.002dB Passband Stopband Passband ripple 0.546fs Stopband attenuation Group delay De-emphasis filter error POWER SUPPLY Supply Range Analog supply, VCC Digital supply, VDD Power down current Power-down supply current, ICC + IDD Quiescent current VCC = +5V, VDD = +3.3V RST = low, system and audio clocks off System and audio clocks applied, all 0s data VCC = +5V, fS =48kHz Analog supply, ICC VCC = +5V, fS =96kHz VCC = +5V, fS =192kHz VDD = +3.3V, fS =48kHz Digital supply, IDD VDD = +3.3V, fS =96kHz VDD = +3.3V, fS =192kHz VCC = +5V, VDD = +3.3V Total power dissipation fS = 48kHz fS = 96kHz fS = 192kHz 203 220 236 256 mW mW mW 32 32 32 13 18 23 17 40 mA mA mA mA mA mA 1 mA +4.75 +3.0 +5.0 +3.3 +5.25 +3.6 V V 0.567fs -75 -82 29/fS 0.1 -3dB 0.546fs 0.002 0.454fS 0.487fS Hz Hz Hz dB dB dB sec dB
CONDITIONS
MIN
TYP
MAX
UNITS
5
PCM4104
www.ti.com SBAS291B - AUGUST 2003 - REVISED MARCH 2004
PIN ASSIGNMENTS TQFP PACKAGE (TOP VIEW)
VOUT2+ VOUT2- VOUT3- VREF2+ VCOM1 VREF3+ VREF2- VREF3- VOUT3+ 38 VCOM2 37 36 VOUT4+ 35 VOUT4- 34 AGND2 33 VREF4- 32 VREF4+ 31 NC 30 NC 29 FS1 28 FS0 27 FMT2 26 FMT1 25 FMT0 24 CDOUT VCC1 VCC2 40 21 CS
48
47
46
45
44
43
42
41
39
VOUT1+ VOUT1- AGND1 VREF1- VREF1+ NC NC MODE RST
1 2 3 4 5 6 7 8 9
PCM4104
MUTE 10 DEM1 11 DEM0 12
13 SUB
14 SCKI
15 BCK
16 LRCK
17 DATA0
18 DATA1
19 VDD
20 DGND
22 CCLK
23 CDIN
Terminal Functions
TERMINAL NAME VOUT1+ VOUT1- AGND1 VREF1- VREF1+ NC NC MODE RST MUTE DEM1 DEM0 SUB SCKI NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Input Input Input Input Input Input Input I/O Output Output Ground Input Input Channel 1 Analog Output, Noninverted Channel 1 Analog Output, Inverted Analog Ground Channel 1 Low Reference Voltage; Connect to AGND Channel 1 High Reference Voltage; Connect to VCC No Internal Connection No Internal Connection Operating Mode (0 = Standalone, 1= Software Controlled) Reset/Power Down (Active Low) All-Channel Soft Mute (Active High) Digital De-Emphasis Filter Configuration Digital De-Emphasis Filter Configuration Sub-Frame Assignment (TDM Formats Only) System Clock DESCRIPTION
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PCM4104
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Terminal Functions (continued)
TERMINAL NAME BCK LRCK DATA0 DATA1 VDD DGND CS CCLK CDIN CDOUT FMT0 FMT1 FMT2 FS0 FS1 NC NC VREF4+ VREF4- AGND2 VOUT4- VOUT4+ VCOM2 VOUT3+ VOUT3- VCC2 VREF3+ VREF3- VREF2- VREF2+ VCC1 VOUT2- VOUT2+ VCOM1 NO. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Input Input Ground Output Output Output Output Output Power Input Input Input Input Power Output Output Output I/O Input Input Input Input Power Ground Input Input Input Output Input Input Input Input Input Audio Bit (or Data) Clock Audio Left/Right (or Word) Clock Audio Data for Channels 1 and 2 (I2S, Left/Right Justified formats) or Audio Data for Channels 1 Through 4 for TDM Formats Audio Data for Channels 3 and 4 (I2S, Left/Right Justified formats) Digital Power Supply, +3.3V Digital Ground Serial Peripheral Interface (SPI) Chip Select (Active Low) Serial Peripheral Interface (SPI) Data Clock Serial Peripheral Interface (SPI) Data Input Serial Peripheral Interface (SPI) Data Output Audio Data Format Configuration Audio Data Format Configuration Audio Data Format Configuration Sampling Mode Configuration Sampling Mode Configuration No Internal Connection No Internal Connection Channel 4 High Reference Voltage; Connect to VCC Channel 4 Low Reference Voltage; Connect to AGND Analog Ground Channel 4 Analog Output, Inverted Channel 4 Analog Output, Noninverted DC Common-Mode Voltage for Channels 3 and 4, +2.5V nominal Channel 3 Analog Output, Noninverted Channel 3 Analog Output, Inverted Analog Power Supply, +5V Channel 3 High Reference Voltage; Connect to VCC Channel 3 Low Reference Voltage,; Connect to AGND Channel 2 Low Reference Voltage; Connect to AGND Channel 2 High Reference Voltage; Connect to VCC Analog Power Supply, +5V Channel 2 Analog Output, Inverted Channel 2 Analog Output, Noninverted DC Common-Mode Voltage for Channels 1 and 2, +2.5V nominal DESCRIPTION
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PCM4104
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TYPICAL CHARACTERISTICS
All parameters are specified at TA = +25C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
FFT PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 48kHz fIN = 1kHz 0dBFS Amplitude 24-Bit Data Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 48kHz fIN = 1kHz -20dBFS Amplitude 24-Bit Data
FFT PLOT
Amplitude (dB)
100
1k Frequency (Hz)
10k 20k
100
1k Frequency (Hz)
10k
20k
FFT PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 48kHz fIN = 1kHz -60dBFS Amplitude 24-Bit Data Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 48kHz Idle Channel Input 24-Bit Data
FFT PLOT
Amplitude (dB)
100
1k Frequency (Hz)
10k
20k
100
1k Frequency (Hz)
10k
20k
FFT PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 96kHz fIN = 1kHz 0dBFS Amplitude 24-Bit Data Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 96kHz fIN = 1kHz -20dBFS Amplitude 24-Bit Data
FFT PLOT
Amplitude (dB)
100
1k Frequency (Hz)
10k
40k
100
1k Frequency (Hz)
10k
40k
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PCM4104
www.ti.com SBAS291B - AUGUST 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
FFT PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 96kHz fIN = 1kHz -60dBFS Amplitude 24-Bit Data Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 96kHz Idle Channel Input 24-Bit Data
FFT PLOT
Amplitude (dB)
100
1k Frequency (Hz)
10k
40k
100
1k Frequency (Hz)
10k
40k
FFT PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 192kHz fIN = 1kHz 0dBFS Amplitude 24-Bit Data Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 192kHz fIN = 1kHz -20dBFS Amplitude 24-Bit Data
FFT PLOT
Amplitude (dB)
100
1k Frequency (Hz)
10k
40k
100
1k Frequency (Hz)
10k
40k
FFT PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 192kHz fIN = 1kHz -60dBFS Amplitude 24-Bit Data Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 192kHz Idle Channel Input 24-Bit Data
FFT PLOT
Amplitude (dB)
100
1k Frequency (Hz)
10k
40k
100
1k Frequency (Hz)
10k
40k
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PCM4104
www.ti.com SBAS291B - AUGUST 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
FFT PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 44.1kHz fIN = 1kHz 0dBFS Amplitude 16-Bit Data Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 44.1kHz fIN = 1kHz -20dBFS Amplitude 16-Bit Data
FFT PLOT
Amplitude (dB)
100
1k Frequency (Hz)
10k
20k
100
1k Frequency (Hz)
10k
20k
FFT PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 44.1kHz fIN = 1kHz -60dBFS Amplitude 16-Bit Data Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 fS = 44.1kHz Idle Channel Input 16-Bit Data
FFT PLOT
Amplitude (dB)
100
1k Frequency (Hz)
10k
20k
100
1k Frequency (Hz)
10k
20k
THD+N vs AMPLITUDE -80 -85 -90 THD+N (dB) -95 -100 -105 -110 -115 -120 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 THD+N (dB) fS = 48kHz fIN = 1kHz 24-Bit Data -80 -85 -90 -95 -100 -105 -110 -115 -120 -150 -140 -130 -120 -110 fS = 96kHz fIN = 1kHz 24-Bit Data
THD+N vs AMPLITUDE
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
Amplitude (dBFS)
Amplitude (dBFS)
10
0
PCM4104
www.ti.com SBAS291B - AUGUST 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
THD+N vs AMPLITUDE -80 -85 -90 -95 THD+N (dB) -100 -105 -110 -115 -120 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 THD+N (dB) fS = 192kHz fIN = 1kHz 24-Bit Data -80 -85 -90 -95 -100 -105 -110 -115 -120 -150 -140 -130 -120 -110 fS = 44.1kHz fIN = 1kHz 16-Bit Data
THD+N vs AMPLITUDE
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10 14
Amplitude (dBFS)
Amplitude (dBFS)
FREQUENCY RESPONSE 0 -20 -40 Amplitude (dB) Amplitude (dB) -60 -80 -100 -120 -140 -160 0 1 2 Frequency (x fS) 3 4 0.003 0.002 0.001 0 -0.001 -0.002 -0.003 0 0.1
PASSBAND RIPPLE
0.2
0.3
0.4
0.5
Frequency (x fS)
DE-EMPHASIS FILTER RESPONSE (fS = 32kHz) 0.0 -1.0 -2.0 -3.0 Level (dB) -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 0 2 4 6 8 10 12 14 Frequency (kHz) Error (dB) -4.0 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 2
DE-EMPHASIS ERROR (f S = 32kHz)
4
6
8
10
12
Frequency (kHz)
0
11
PCM4104
www.ti.com SBAS291B - AUGUST 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
DE-EMPHASIS FILTER RESPONSE (fS = 44.1kHz) 0.0 -1.0 -2.0 -3.0 Level (dB) -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 0 2 4 6 8 10 12 14 16 18 20 Frequency (kHz) Error (dB) -4.0 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 2
DE-EMPHASIS ERROR (f S = 44.1kHz)
4
6
8
10
12
14
16
18
20
Frequency (kHz)
DE- EMPHASIS FILTER RESPONSE (fS = 48kHz) 0.0 -1.0 -2.0 -3.0 Level (dB) -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 0 2 4 6 8 10 12 14 16 18 22 Frequency (kHz) Error (dB) -4.0 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 2
DE- EMPHASIS ERROR (fS = 48kHz)
4
6
8
10
12
14
16
18
22
Frequency (kHz)
12
PCM4104
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PRODUCT OVERVIEW
The PCM4104 is a high-performance, four-channel D/A converter designed for professional audio systems. The PCM4104 supports 16- to 24-bit linear PCM input data and sampling frequencies up to 200kHz. The PCM4104 utilizes an 8x oversampling digital interpolation filter, followed by a multi-level delta-sigma modulator with a single pole switched capacitor output filter. This architecture provides excellent dynamic and sonic performance, as well as high tolerance to clock phase jitter. Functional block diagrams, showing both Standalone and Software modes, are shown in Figure 1 and Figure 2. The PCM4104 incorporates a flexible audio serial port, which accepts 16- to 24-bit PCM audio data in both standard audio formats (Left Justified, Right Justified, and Philips I2S) and TDM data formats. The TDM formats are especially useful for interfacing to the synchronous serial ports of digital signal processors. The TDM formats support daisy-chaining of two PCM4104 devices on a single three-wire serial interface (for sampling frequencies up to 100kHz), forming a high-performance eight-channel D/A conversion system. The PCM4104 offers two modes for configuration control: Software and Standalone. Software mode makes use of a four-wire SPI port to access internal control registers, allowing configuration of the full PCM4104 feature set. Standalone mode offers a more limited subset of the functions available in Software mode, while allowing for a simplified pin-programmed configuration mode.
VREF1+ D/A Converter and Output Filter VOUT1+ VOUT1- VREF1- VCOM1 VREF2+ D/A Converter and Output Filter Digital Filtering and Functions D/A Converter and Output Filter VOUT2+ VOUT2- VREF2- VREF3+ VOUT3+ VOUT3- VREF3- VCOM2 VREF4+ SCKI System Clock and Timing D/A Converter and Output Filter VOUT4+ VOUT4- VREF4- VDD DGND VCC 1 AGND1 VCC21 AGND2
LRCK BCK DATA0 DATA1
Audio Serial Port
RST MUTE DEM0 DEM1 SUB FMT0 FMT1 FMT2 FS0 FS1 MODE
Control
Digital Power
Analog Power
Figure 1. Functional Block Diagram for Standalone Mode
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VREF1+ D/A Converter and Output Filter VOUT1+ VOUT1- VREF1- VCOM1 VREF2+ D/A Converter and Output Filter RST MUTE SUB CS CCLK CDIN CDOUT MODE VDD Digital Filtering and Functions D/A Converter and Output Filter VOUT2+ VOUT2- VREF2- VREF3+ VOUT3+ VOUT3- VREF3- VCOM2 VREF4+ SCKI System Clock and Timing D/A Converter and Output Filter VOUT4+ VOUT4- VREF4- VDD DGND VCC1 AGND1 VCC21 AGND2
LRCK BCK DATA0 DATA1
Audio Serial Port
Control and SPI Port
Digital Power
Analog Power
Figure 2. PCM4104 Functional Block Diagram for Software Mode ANALOG OUTPUTS
The PCM4104 provides four differential voltage outputs, corresponding to audio channels 1 through 4. VOUT1+ (pin 1) and VOUT1- (pin 2) correspond to Channel 1. VOUT2+ (pin 47) and VOUT2- (pin 46) correspond to Channel 2. VOUT3+ (pin 38) and VOUT3- (pin 39) correspond to Channel 3. VOUT4+ (pin 36) and VOUT4- (pin 35) correspond to Channel 4. Each differential output is typically capable of providing 6.15V full-scale (differential) into a 600 output load. The output pins are internally biased to the common-mode (or bipolar zero) voltage, which is nominally VCC/2. The output section of each D/A converter channel includes a single-pole, switched capacitor low-pass filter circuit. The switched capacitor filter response tracks with the sampling frequency of the D/A converter and provides attenuation of the out-of-band noise produced by the delta-sigma modulator. An external two-pole continuous time filter is recommended to further reduce the out-of-band noise energy and to band limit the output spectrum to frequencies suitable for audio reproduction. Refer to the Applications Information section of this data sheet for recommended output filter circuits.
VOLTAGE REFERENCES
The PCM4104 includes high and low reference pins for each output channel. VREF1+ (pin 5) and VREF1- (pin 4) correspond to Channel 1. VREF2+ (pin 44) and VREF2- (pin 43) correspond to Channel 2. VREF3+ (pin 41) and VREF3- (pin 42) correspond to Channel 3. VREF4+ (pin 32) and VREF4- (pin 33) correspond to Channel 4. The high reference (+) pin may be connected to the corresponding VCC supply or an external +5.0V reference, while the low reference (-) pin is connected to analog ground. A 0.01F bypass capacitor should be placed
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between the corresponding high and low reference pins. An X7R ceramic chip capacitor is recommended for this purpose. In some cases, a larger capacitor may need to be placed in parallel with the 0.01F capacitor, with the value of the larger capacitor being dependent upon the low-frequency power-supply noise present in the system. Typical values may range from 1F to 10F. Low ESR tantalum or multilayer ceramic chip capacitors are recommended. Figure 3 illustrates the recommended connections for the reference pins.
VCC VREF+(1) 0.01F VREF - (1) 0.1F to 10F
SAMPLING MODES
The PCM4104 can operate in one of three sampling modes: Single Rate, Dual Rate, or Quad Rate. Sampling modes are selected by using the FS[1:0] bits in Control Register 6 in Software mode, or by using the FS0 (pin 28) and FS1 (pin 29) inputs in Standalone mode. The Single Rate mode allows sampling frequencies up to and including 50kHz. The D/A converter performs 128x oversampling of the input data in Single Rate mode. The Dual Rate mode allows sampling frequencies greater than 50kHz, up to and including 100kHz. The D/A converter performs 64x oversampling of the input data in Dual Rate mode. The Quad Rate mode allows sampling frequencies greater than 100kHz, up to and including 200kHz. The D/A converter performs 32x oversampling of the input data in Quad Rate mode.
VCOM1 VCOM2 0.1F 0.1F
Refer to Table 1 for examples of system clock requirements for common sampling frequencies.
SYSTEM CLOCK REQUIREMENTS
(1) Capacitor(s) required for each of the four reference pairs.
Figure 3. Recommended Connections for Voltage Reference and Common-Mode Output Pins
In addition to the reference pins, there are two common-mode voltage output pins, VCOM1 (pin 48) and VCOM2 (pin 37). These pins are nominally set to a value equal to VCC/2 by internal voltage dividers. The VCOM1 pin is common to both Channels 1 and 2, while the VCOM2 pin is common to Channels 3 and 4. A 0.1F X7R ceramic chip capacitor should be connected between the common-mode output pin and analog ground. The common-mode outputs are used primarily to bias external output circuitry.
The PCM4104 requires a system clock, applied at the SCKI (pin 14) input. The system clock operates at an integer multiple of the input sampling frequency, or fS. The multiples supported include 128fS, 192fS, 256fS, 384fS, 512fS, or 768fS. The system clock frequency is dependent upon the sampling mode. Table 1 shows the required system clock frequencies for common audio sampling frequencies. Figure 4 shows the system clock timing requirements. Although the architecture of the PCM4104 is tolerant to phase jitter on the system clock, it is recommended that the user provide a low jitter clock (100 picoseconds or less) for optimal performance.
Table 1. Sampling Modes and System Clock Frequencies for Common Audio Sampling Rates
SAMPLING MODE SAMPLING FREQUENCY, fS (kHz) 32 44.1 48 88.2 96 176.4 192 SYSTEM CLOCK FREQUENCY (MHz) 128fS n/a n/a n/a n/a n/a 22.5792 24.576 192fS n/a n/a n/a n/a n/a 33.8688 36.864 256fS 8.192 11.2896 12.288 22.5792 24.576 n/a n/a 384fS 12.288 16.9344 18.432 33.8688 36.864 n/a n/a 512fS 16.384 22.5792 24.576 n/a n/a n/a n/a 768fS 24.576 33.8688 36.864 n/a n/a n/a n/a
Single Rate Single Rate Single Rate Dual Rate Dual Rate Quad Rate Quad Rate
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t SCKIH
SCKI
t SCKIL
t SCKI
PARAMETER t SCKI t SCKIH t SCKIL
DESCRIPTION System Clock Period System Clock High Pulse Time System Clock Low Pulse Time
MIN 26 12 12
MAX
UNITS ns ns ns
Figure 4. System Clock Timing Requirements RESET OPERATION
The PCM4104 includes three reset functions: power-on, external, and software-controlled. This section describes each of the three reset functions. On power up, the internal reset signal is forced low, forcing the PCM4104 into a reset state. The power-on reset circuit monitors the VDD, VCC1, and VCC2 power supplies. When VDD exceeds +2.0V (margin of error is 400mV) and VCC1 and VCC2 exceed +4.0V (margin of error is 400mV), the internal reset signal is forced high. The PCM4104 then waits for the system clock input (SCKI) to become active. Once the system clock has been detected, the initialization sequence begins. The initialization sequence requires 1024 system clock periods for completion. When the initialization sequence is completed, the PCM4104 is ready to accept audio data at the audio serial port. Figure 5 shows the power-on reset sequence timing. If the PCM4104 is configured for Software mode control via the SPI port, all control registers will be reset to their default state during the initialization sequence. In both Standalone and Software modes, the analog outputs for all four channels are muted during the reset and initialization sequence. While in mute state, the analog output pins are driven to the bipolar zero voltage, or VCC/2. The user may force a reset initialization sequence at any time while the system clock input is active by utilizing the RST input (pin 9). The RST input is active low, and requires a minimum low pulse width of 40 nanoseconds. The low-to-high transition of the applied reset signal will force an initialization sequence to begin. As in the case of the power-on reset, the initialization sequence requires 1024 system clock periods for completion. Figure 6 illustrates the reset sequence initiated when using the RST input. A reset initialization sequence is available in Software mode, using the RST bit in Control Register 6. The RST bit is active high. When RST is set to 1, a reset sequence is initiated in the same fashion as an external reset applied at the RST input. Figure 7 shows the state of the analog outputs for the PCM4104 before, during and after the reset operations.
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~ 4.0V VCC1 VCC2 0V
VDD
~ 2.0V 0V
Internal Reset
0V
1024 System Clock Periods Required for Initialization
SCKI 0V System Clock Indeterminate or Inactive
Figure 5. Power-Up Reset Timing
t RSTL > 40ns
RST 0V
Internal R eset 0V
1 02 4 Sy s tem C loc k Pe riods R equ ire d fo r In itializa tion
SC K I 0V
Figure 6. External Reset Timing
Internal Reset
HI LO Outputs are Muted for 1024 SCKI Periods Initialization Period
Analog Outputs
Outputs are On
Outputs are Muted
Outputs are On
Figure 7. Analog Output State for Reset Operations
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POWER-DOWN OPERATION
The PCM4104 can be forced to a power-down state by applying a low level to the RST input for a minimum of 65,536 system clock cycles. In power-down mode, all internal clocks are stopped, and analog outputs are set to a high-impedance state. The system clock can then be removed to conserve additional power. In the case of system clock restart when exiting the power-down state, the clock should be restarted prior to a low-to-high transition of the reset signal at the RST input. The low-to-high transition of the reset signal initiates a reset sequence, as described in the Reset Operation section of this data sheet. In Software mode, two additional power-down controls are provided. The PDN12 and PDN34 bits are located in Control Register 6 and may be used to power-down channel pairs, with PDN12 corresponding to channels 1 and 2, and PDN34 corresponding to channels 3 and 4.
This allows the user to conserve power when a channel pair is not in use. The power-down function is the same as described in the previous paragraph for the corresponding channel pair. Unlike the power-down function implemented using the RST input, setting a power-down bit will immediately power down the corresponding channel pair. When exiting power-down mode, either by forcing the RST input high or by setting the PDN12 or PDN34 bits low, the analog outputs will transition from the high-impedance state to the mute state, with the output level set to the bipolar zero voltage. There may be a small transient created by this transition, since internal capacitor charge can initially force the output to a voltage above or below bipolar zero, or external circuitry can pull the outputs to some other voltage level. Figure 8 illustrates the state of the analog outputs before, during, and after a power-down event.
VDD RST 0V
Analog Outputs
Outputs are On
Outputs are Muted
Outputs are High Impedance
Outputs Transition from High Impedance to Muted State
Outputs are On
65,536 SCKI Periods
1024 SCKI Periods Required for Initialization
HI PDN12 PDN34
LO
Analog Outputs
Outputs are On
Outputs are High Impedance
Outputs Transition from High Impedance to Muted State
Outputs are On
1024 SCKI Periods Required for Initialization
Outputs are On Transitioning to Driven State
Figure 8. Analog Output State for Power-Down Operations
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AUDIO SERIAL PORT
The audio serial port provides a common interface to digital signal processors, digital interface receivers (AES3, S/PDIF), and other digital audio devices. The port operates as a slave to the processor, receiver, or other clock generation circuitry. Figure 9 illustrates a typical audio serial port connection to a processor or receiver. The audio serial port is comprised of four signal pins: BCK (pin 15), LRCK (pin 16), DATA0 (pin 17), and DATA1 (pin 18).
The DATA0 and DATA1 pins are the audio data inputs. When using Left Justified, Right Justified, or I2S data formats, the DATA0 pin carries the audio data for channels 1 and 2, while the DATA1 pin carries the audio data for channels 3 and 4. When using TDM data formats, DATA0 carries the audio data for all four channels, while the DATA1 input is ignored. The audio serial port data formats are shown in Figure 10, Figure 13, and Figure 14. Data formats are selected by using the FMT[2:0] bits in Control Register 7 in Software mode, or by using the FMT0 (pin 25), FMT1 (pin 26), and FMT2 (pin 27) inputs in Standalone mode. In Software mode, the user may also select the phase (normal or inverted) for the LRCK input, as well as the data sampling edge for the BCK input (either rising or falling edge). The reset default conditions for the Software mode are normal phase for LRCK and rising edge data sampling for BCK. The Left Justified, Right Justified, and I2S data formats are similar to one another, with differences in data justification and word length. The PCM audio data must be two's complement binary, MSB first. Figure 10 provides illustrations for these data formats. The TDM formats carry the information for four or eight channels on a single data line. The DATA0 input (pin 17) is used as the data input for the TDM formats. The data is carried in a time division multiplexed fashion, hence the TDM acronym used to describe this format. Figure 12 shows the TDM connection of two PCM4104 devices. The data for each channel is assigned one of the time slots in the TDM frame, as shown in Figure 13 and Figure 14. The sub-frame assignment for each PCM4104 is determined by the state of the SUB input (pin 13). When SUB is forced low, the device is assigned to sub-frame 0. When SUB is forced high, the device is assigned to sub-frame 1.
DSP FSX CLKX DX0 DX1
PCM4104 LRCK BCK DATA0 DATA1 SCKI
System Clock
Figure 9. Audio Serial Port Connections for Left Justified, Right Justified, and I2S Formats.
The LRCK pin functions as either the left/right word clock or the frame synchronization clock, depending upon the data format selected. The LRCK frequency is equal to the input sampling frequency (44.1kHz, 48kHz, 96kHz, etc.). The BCK pin functions as the serial data clock input. This input is referred to as the bit clock. The bit clock runs at an integer multiple of the input sampling frequency. Typical multiples include 32, 48, 64, 96, 128, 192, and 256, depending upon the data format, word length, and system clock frequency selected.
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Ch. 1 (DATA0) or Ch. 3 (DATA1) LRCK BCK DATA0 DATA1 MSB LSB MSB
Ch. 2 (DATA0) or Ch. 4 (DATA1)
LSB
(a) Left-Justified Data Format
LRCK BCK DATA0 DATA1 MSB LSB (b) Right-Justified Data Format LRCK BCK DATA0 DATA1
MSB
MSB
LSB
LSB (c) I2S
MSB Data Format 1/fS
LSB
Figure 10. Left Justified, Right Justified, and I2S Data Formats
LRCK t LRBKD BCK (BCKE = 0) t BCKHL BCK (BCKE = 1) t BCKP t BKLRD
DATA0 DATA1 t DS t DH
PA R A M E TER
D ES C R IP T IO N
M IN
MAX
U N ITS
t BCKP t BCKHL t LRBKD t BKLRD t DS t DH
-
BCK Cycle Time BCK High/Low Time LRCK Edge to BCK Sampling Edge Delay BCK Sampling Edge to LRCK Edge Delay Data Setup Time Data Hold Time LRCK Duty Cycle
70 30 10 10 10 10 50
ns ns ns ns ns ns %
Figure 11. Audio Serial Port Timing for Left Justified, Right Justified, and I2S Data Formats.
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Device #1 (Sub-Frame 0) DSP FSX CLKX DX PCM4104 LRCK BCK DATA0 SUB SCKI
Device #2 (Sub-Frame 1) PCM4104 LRCK BCK DATA0 SUB VCC System Clock
Figure 12. TDM Connection
TDM Data Formats - Long Frame Supported for Single and Dual Rate Sampling Modes Only
LRCK Normal, Zero BCK Delay LRCK Normal, One BCK Delay
LRCK Inverted, Zero BCK Delay LRCK Inverted, One BCK Delay DATA0 Supports 8 Channels, or two PCM4104 devices. Slot 1 Ch. 1 Slot 2 Ch. 2 Slot 3 Ch. 3 Slot 4 Ch. 4 Slot 5 Ch. 1 Slot 6 Ch. 2 Slot 7 Ch. 3 Slot 8 Ch. 4
Sub-Frame 0 (SUB = 0) One Frame BCK = 192f S or 256fS
Sub-Frame 1 (SUB = 1)
In the case of BCK = 192fS , each time slot is 24 bits long and contains the 24-bit audio data for the corresponding channel. In the case of BCK = 256fS , each time slot is 32 bits long and contains the 24-bit audio data for the corresponding channel. The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don't care bits. Audio data is always presented in two's complement, MSB-first format.
Figure 13. TDM Data Formats: Long Frame
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TDM Data Formats - Short Frame All Sampling Modes Supported
LRCK Normal, Zero BCK Delay LRCK Normal, One BCK Delay
LRCK Inverted, Zero BCK Delay LRCK Inverted, One BCK Delay DATA0 Supports 4 Channels, or one PCM4104 device.
Slot 1 Ch. 1
Slot 2 Ch. 2
Slot 3 Ch. 3
Slot 4 Ch. 4
One Frame BCK = 96fS or 128fS (the SUB pin is ignored when using a Short Frame) In the case of BCK = 96fS, each time slot is 24 bits long and contains the 24-bit audio data for the corresponding channel. In the case of BCK = 128fS, each time slot is 32 bits long and contains the 24-bit audio data for the corresponding channel. The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don't care bits. Audio data is always presented in two's complement, MSB-first format.
Figure 14. TDM Data Formats: Short Frame
One Frame t LRCKP LRCK t BKBF t LRBKD BCK (BCKE = 0) t BNF
BCK (BCKE = 1)
DATA0 t DS t DH
PA R A M E T ER D E SC R IPT IO N M IN MAX U N IT S
t LRCKP t LRBKD t DS t DH t BNF t BKBF
LRCK pulse width LRCK active edge to BCK sampling edge delay Data setup time Data hold time LRCK transition before new frame BCK sampling edge to new frame delay
1/fBCK 12 10 10 1/fBCK 12
ns ns ns ns ns ns
Figure 15. TDM Timing
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STANDALONE MODE CONFIGURATION
Standalone mode is selected by forcing the MODE input (pin 8) low. Standalone mode operation provides a subset of the functions available in Software mode, while providing an option for a simplified control model. Standalone configuration is accomplished by either hardwiring or driving a small set of input pins with external logic or switches. Standalone mode functions include sampling mode and audio data format selection, an all-channel soft mute function, and digital de-emphasis filtering. The following paragraphs provide a brief description of each function available when using Standalone mode.
Soft Mute Function
The MUTE input (pin 10) may be used in either the Standalone or Software modes to simultaneously mute the four output channels. The soft mute function slowly ramps the digital output attenuation from its current setting to the mute level, minimizing or eliminating audible artifacts. Table 4 summarizes MUTE function operation.
Table 4. Mute Function Configuration
MUTE 0 1 ANALOG OUTPUTS On (mute disabled) Muted
Sampling Mode
The sampling mode is selected using the FS0 (pin 28) and FS1 (pin 29) inputs. A more detailed discussion of the sampling modes was provided in an earlier section of this data sheet. Table 2 summarizes the sampling mode configuration for Standalone mode.
Digital De-Emphasis
This is a global digital function (common to all four channels) and provides de-emphasis of the higher frequency content within the 20kHz audio band. De-emphasis is required when the input audio data has been pre-emphasized. Pre-emphasis entails increasing the amplitude of the higher frequency components in the 20kHz audio band using a standardized filter function in order to enhance the high-frequency response. The PCM4104 de-emphasis filters implement the standard 50/15s de-emphasis transfer function commonly used in digital audio applications. De-emphasis filtering is available for three input sampling frequencies in Single Rate sampling mode: 32kHz, 44.1kHz, and 48kHz. De-emphasis is not available when operating in Dual or Quad Rate sampling modes. The de-emphasis filter is selected using the DEM0 (pin 12) and DEM1 (pin 11) inputs. Table 5 illustrates the de-emphasis filter configuration for Standalone mode.
Table 2. Sampling Mode Configuration
FS1 0 0 1 1 FS0 0 1 0 1 SAMPLING MODE Single Rate Dual Rate Quad Rate - Not Used -
Audio Data Format
The audio data format is selected using the FMT0 (pin 25), FMT1 (pin 26), and FMT2 (pin 27) inputs. A detailed discussion of the audio serial port operation and the corresponding data formats was provided in the Audio Serial Port section on page 19. For Standalone mode, the LRCK polarity is always normal, while the serial audio data is always sampled on the rising edge of the BCK clock. Table 3 shows the audio data format configuration for Standalone mode.
Table 5. Digital De-Emphasis Configuration
DEM1 0 0 1 DEM0 0 1 0 1 DIGITAL DE-EMPHASIS MODE Off (de-emphasis disabled) 48kHz 44.1kHz 32kHz
Table 3. Audio Data Format Configuration
FMT2 0 0 0 0 1 1 1 1 FMT1 0 0 1 1 0 0 1 1 FMT0 0 1 0 1 0 1 0 1 AUDIO DATA FORMAT 24-bit left-justified 24-bit I2S TDM with zero BCK delay TDM with one BCK delay 24-bit right-justified 20-bit right-justified 18-bit right-justified 16-bit right-justified
1
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SOFTWARE MODE CONFIGURATION
Software mode is selected by forcing the MODE input (pin 8) high. Software mode operation provides full access to the features of the PCM4104 by allowing the writing and reading of on-chip control registers. This is accomplished using the four-wire SPI port. The following paragraphs provide a brief description of each function available when using Software mode.
Output Phase Reversal
The PCM4104 includes an output phase reversal function, which provides the ability to invert the output phase for all four channels, either for testing or for matching various output circuit configurations. This function is controlled using the PHASE bit, located within Control Register 5. The output phase is set to noninverted by default on power up or reset.
Digital Attenuation
The audio signal for each channel can be attenuated in the digital domain using this function. Attenuation settings from 0dB (unity gain) to -119.5dB are provided in 0.5dB steps. In addition, the attenuation level may be set to the mute state. The rate of change for the digital attenuation function is one 0.5dB step for every eight LRCK periods. Each channel has its own independent attenuation control, accessed using control registers 1 through 4. The reset default setting for all channels is 0dB, or unity gain (no attenuation applied).
Sampling Mode
Sampling mode configuration was discussed earlier in this data sheet, with Table 1 providing a reference for common sampling and system clock frequencies. The FS0 and FS1 bits located in Control Register 6 are used to set the sampling mode. The sampling mode defaults to Single Rate on power up or reset.
Power-Down Modes
The power-down control bits are located in Control Register 6. These bits are used to power down pairs of D/A converters within the PCM4104. The PDN12 bit is used to power down channels 1 and 2, while the PDN34 bit is used to power down channels 3 and 4. When a channel pair is powered down, it ignores the audio data inputs and sets its outputs to a high-impedance state. By default, the power-down bits are disabled on power up or reset.
Digital De-Emphasis
The de-emphasis function is accessed through Control Register 5 using the DEM[1:0] bits. The reset default setting is that the de-emphasis is disabled for all four channels. De-emphasis filter operation is described in the Standalone Mode Configuration section of this data sheet.
Software Reset
This reset function allows a reset sequence to be initiated under software control. All control registers are reset to their default state. The reset bit, RST, is located in Control Register 6. Setting this bit to 1 initiates a one-time reset sequence. The RST bit is cleared by the initialization sequence.
Soft Mute
Each of the four D/A converter channels has its own independent soft mute control, located in Control Register 5. The reset default is normal output for all four channels with the soft mute function disabled. The MUTE input (pin 10) also functions in Software mode, with a high input forcing soft mute on all four channels.
Audio Data Formats, LRCK Polarity, and BCK Sampling Edge
Control Register 7 is used to configure the PCM4104 audio serial port. Audio serial port operation was discussed previously in this data sheet; refer to that section for more details regarding the functions controlled by this register. The control register definitions provide additional information regarding the register functions and their default settings.
Zero Data Mute
The PCM4104 includes a zero data detection and mute function in Software mode. This function automatically mutes a given channel when 1024 consecutive LRCK periods of all zero data are detected for that channel. The zero data mute function is enabled and disabled using the ZDM bit in Control Register 5. The zero data mute function is disabled by default on power up or reset.
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SERIAL PERIPHERAL INTERFACE (SPI) PORT OPERATION
The SPI port is a four-wire synchronous serial interface that is used to access the on-chip control registers when the PCM4104 is configured for Software mode operation. The CDIN input (pin 23) is the serial data input for the port, while CDOUT (pin 24) is used for reading back control register contents in a serial fashion. The CS input (pin 21) functions as the chip select input, and must be forced low for register write or read access. The CCLK input (pin 22) functions as the serial data clock, used to clock data in and out of the port. Data is clocked into the port on the rising edge of CCLK, while data is clocked out of the port on the falling edge of CCLK. There are three modes of operation supported for the SPI port: Single Register, Continuous, and Auto-Increment. The Single Register and Continuous modes are similar to one another. In Continuous mode, instead of bringing the CS input high after writing or reading a single register, the CS input is held low and a new control byte is issued with a new address for the next write or read operation. Continuous mode allows multiple, sequential or nonsequential register addresses to be read or written in succession, as shown in Figure 16. Auto-Increment mode is designed for writing or reading multiple sequential register addresses. After the first register is written or read, the register address is
automatically incremented by 1, so the next write or read operation is performed without issuing another control byte, as shown in Figure 17.
Control Byte (or Byte 0)
The control byte, or byte 0, is the first byte written to the PCM4104 SPI port when performing a write or read operation. The control byte includes bits that define the operation to be performed (read or write), the auto-increment mode status, and the control register address. The Read/Write bit, R/W, is set to 0 to indicate a register write operation, or set to 1 for a register read operation. The Increment bit, INC, enables or disables the Auto-Increment mode of operation. When this bit is set to a 0, auto-increment operation is disabled, and the operation performed is either Single Register or Continuous. Setting the INC bit to 1 enables Auto-Increment operation. A two-bit key code, 10B, follows the INC bit and must be present in order for any operation to take place on the control port. Any other combination for these bits will result in the port ignoring the write or read request. The four-bit address field, A[3:0], is used to specify the control register address for the read or write operation, or the starting address for an Auto-Increment write or read operation.
Set CS = 1 here for Single Register Operations
Keep CS = 0 for writing or reading multiple registers in Continuous mode
CS Control Byte CDIN CDOUT CCLK byte 0 High Impedance Register Data byte 1 Register Data byte 1 High Impedance Control Byte byte 0 Register Data byte 1 Register Data byte 2 byte N byte N
Control Byte Definition (Byte 0)
MSB R/W INC 1 0 A3 A2 A1 LSB A0
Register Address Auto - Increment Control: Set to 0 for Single Register or Continuous Operation
Read/WriteControl: 0 = Write 1 = Read
Figure 16. Single Register and Continuous Write or Read Operation
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Keep CS = 0 for Auto-Increment Operation CS Control Byte CDIN byte 0 Register Data byte 1 Register Data CDOUT CCLK High Impedance byte 1 byte 2 byte 3 byte N byte 2 byte 3 byte N
Control Byte Definition (Byte 0)
MSB R/W INC 1 0 A3 A2 A1 LSB A0
Register Address Auto- Increment Control: Set to 1 for Auto-Increment Operation Read/WriteControl: 0 = Write 1 = Read
Figure 17. Auto-Increment Write or Read Operation
tDS CSB
tDH
tCH
CCLK
CDIN
MSB
CDOUT
High Impedance (Hi Z) t DO
MSB
LSB tCSZ
Hi Z
PARAMETER tDS tDH tCH t DO tCSZ
DESCRIPTION CDIN Data Setup Time CDIN Data Hold Time CSB Hold Time CDOUT Data Delay Time CSB High to CDOUT Hi Z
MIN 5 2 2
MAX
UNIT ns ns ns
5 5
ns ns
Figure 18. SPI Port Timing
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CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY)
The PCM4104 includes a small set of control registers, which are utilized to configure the full set of on-chip functions in Software mode. The register map is shown in Table 6. Register 0 is reserved for factory use and should not be written to for normal operation. Register 0 defaults to all zero data on power up or reset.
Table 6. Control Register Map
CONTROL REGISTER ADDRESS (HEX) 0 1 2 3 4 5 6 7 MSB BIT 7 0 AT17 AT27 AT37 AT47 MUT4 RST 0 BIT 6 0 AT16 AT26 AT36 AT46 MUT3 0 0 BIT 5 0 AT15 AT25 AT35 AT45 MUT2 0 BCKE BIT 4 0 AT14 AT24 AT34 AT44 MUT1 0 LRCKP BIT 3 0 AT13 AT23 AT33 AT43 ZDM PDN34 0 BIT 2 0 AT12 AT22 AT32 AT42 PHASE PDN12 FMT2 BIT 1 0 AT11 AT21 AT31 AT41 DEM1 FS1 FMT1 LSB BIT 0 0 AT10 AT20 AT30 AT40 DEM0 FS0 FMT0
Register 1: Attenuation Control Register - Channel 1
BIT 7 (MSB) AT17 BIT 6 AT16 BIT 5 AT15 BIT 4 AT14 BIT 3 AT13 BIT 2 AT12 BIT 1 AT11 BIT 0 (LSB) AT10
This register controls the digital output attenuation for Channel 1. Default: AT1[7:0] = 255, or 0dB Let N = AT1[7:0]. For N = 16 to 255, Attenuation (dB) = 0.5 x (255 - N) For N = 0 to 15, Attenuation (dB) = Infinite (Muted)
Register 2: Attenuation Control Register - Channel 2
BIT 7 (MSB) AT27 BIT 6 AT26 BIT 5 AT25 BIT 4 AT24 BIT 3 AT23 BIT 2 AT22 BIT 1 AT21 BIT 0 (LSB) AT20
This register controls the digital output attenuation for Channel 2. Default: AT2[7:0] = 255, or 0dB Let N = AT2[7:0]. For N = 16 to 255, Attenuation (dB) = 0.5 x (255 - N) For N = 0 to 15, Attenuation (dB) = Infinite (Muted)
Register 3: Attenuation Control Register - Channel 3
BIT 7 (MSB) AT37 BIT 6 AT36 BIT 5 AT35 BIT 4 AT34 BIT 3 AT33 BIT 2 AT32 BIT 1 AT31 BIT 0 (LSB) AT30
This register controls the digital output attenuation for Channel 3. Default: AT3[7:0] = 255, or 0dB Let N = AT3[7:0]. For N = 16 to 255, Attenuation (dB) = 0.5 x (255 - N) For N = 0 to 15, Attenuation (dB) = Infinite (Muted)
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PCM4104
www.ti.com SBAS291B - AUGUST 2003 - REVISED MARCH 2004
Register 4: Attenuation Control Register - Channel 4
BIT 7 (MSB) AT47 BIT 6 AT46 BIT 5 AT45 BIT 4 AT44 BIT 3 AT43 BIT 2 AT42 BIT 1 AT41 BIT 0 (LSB) AT40
This register controls the digital output attenuation for Channel 4. Default: AT4[7:0] = 255, or 0dB Let N = AT4[7:0]. For N = 16 to 255, Attenuation (dB) = 0.5 x (255 - N) For N = 0 to 15, Attenuation (dB) = Infinite (Muted)
Register 5: Function Control Register
BIT 7 (MSB) MUT4 BIT 6 MUT3 BIT 5 MUT2 BIT 4 MUT1 BIT 3 ZDM BIT 2 PHASE BIT 1 DEM1 BIT 0 (LSB) DEM0
This register controls various D/A converter functions, including de-emphasis filtering, output phase reversal, zero data mute, and per-channel soft muting.
DEM[1:0]
Digital De-Emphasis
De-emphasis is available for Single Rate mode only. De-emphasis is disabled for Dual and Quad Rate modes. DEM1 0 0 1 1 DEM0 0 1 0 1 De-Emphasis Selection De-emphasis disabled (default) De-emphasis for fS = 48kHz De-emphasis for fS = 44.1kHz De-emphasis for fS = 32kHz
PHASE
Output Phase
PHASE 0 1 Output Phase Noninverted (default) Inverted
ZDM
Zero Data Mute
ZDM 0 1 Zero Mute Disabled (default) Enabled
MUT[4:1]
Soft Mute
MUTx 0 1 D/A Converter Output On (default) Muted
NOTE: x = channel number.
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PCM4104
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Register 6: System Control Register
BIT 7 (MSB) RST BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 PDN34 BIT 2 PDN12 BIT 1 FS1 BIT 0 (LSB) FS0
This register controls various system level functions of the PCM4104, including sampling mode, power down, and soft reset.
FS[1:0]
Sampling Mode
FS1 0 0 1 1 FS0 0 1 0 1 Sampling Mode Single Rate (default) Dual Rate Quad Rate - Not Used -
PDN12
Power-Down for Channels 1 and 2
PDN12 0 1 Power Down for Channels 1 and 2 Disabled (default) Enabled
PDN34
Power Down for Channels 3 and 4
PDN34 0 1 Power Down for Channels 3 and 4 Disabled (default) Enabled
RST
Software Reset (value defaults to 0)
Setting this bit to 1 will initiate a logic reset of the PCM4104. This bit functions the same as an external reset applied at the RST input (pin 9).
Register 7: Audio Serial Port Control Register
BIT 7 (MSB) 0 BIT 6 0 BIT 5 BCKE BIT 4 LRCKP BIT 3 0 BIT 2 FMT2 BIT 1 FMT1 BIT 0 (LSB) FMT0
This register is used to control the data format and clock polarity for the PCM4104 audio serial port.
FMT[2:0]
Audio Data Format
FMT2 0 0 0 0 1 1 1 1 FMT1 0 0 1 1 0 0 1 1 DEM0 Data Format 0 1 0 1 0 1 0 1 24-bit left-justified (default) 24-bit I2S TDM with zero BCK delay TDM with one BCK delay 24-bit right-justified 20-bit right-justified 18-bit right-justified 16-bit right-justified
LRCKP BCKE
LRCK Polarity (0 = Normal, 1 = Inverted). Defaults to 0. BCK Sampling Edge (0 = Rising Edge, 1 = Falling Edge), Defaults to 0.
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APPLICATIONS INFORMATION
This section provides practical information for system and hardware engineers that are designing in the PCM4104. The configuration of the output filter circuit is dependent upon whether a single-ended or differential output is required. Single-ended outputs are commonly used in consumer playback systems, while differential or balanced outputs are used in many professional audio applications, such as recording or broadcast studios and live sound systems. Figure 21 illustrates an active filter circuit that uses a single op amp to provide both 2nd-order low-pass filtering and differential to single-ended signal conversion. This circuit is used on the PCM4104EVM evaluation circuit and meets the published typical Electrical Characteristics for dynamic performance. The single-ended output is convenient for connecting to both headphone and power amplifiers when used for listening tests. The quality of the op amp used is this circuit is important, as many devices will degrade the dynamic range and/or total harmonic distortion plus noise (THD+N) specifications for the PCM4104. An NE5534A is shown in Figure 21 and provides both low noise and distortion. Bipolar input op amps with equivalent specifications should produce similar measurement results. Devices that exhibit higher equivalent input noise voltage, such as the Texas Instruments OPA134 or OPA604 families, will produce lower dynamic range measurements (approximately 1dB to 2dB lower than the typical PCM4104 specification), while having little or no impact on the THD+N specification when measuring a full-scale output level. Figure 22 illustrates a fully-differential output filter circuit suitable for use with the PCM4104. The OPA1632 from Texas Instruments provides the fully differential signal path in this circuit. The OPA1632 features very low noise and distortion, making it suitable for high-end audio applications. Texas Instruments provides a free software tool, FilterProt, used to assist in the design of active filter circuits. The software supports design of multiple feedback (MFB), Sallen-Key, and fully differential filter circuits. FilterPro is available from the TI web site. Additionally, TI document number SBAF001A, also available from the TI web site, provides pertinent application information regarding the proper usage of the FilterPro program.
BASIC CIRCUIT CONFIGURATIONS
Figure 19 and Figure 20 show typical circuit configurations for the PCM4104 operated in Standalone and Software modes. Power supply bypass and reference decoupling capacitors should be placed as close to the corresponding PCM4104 pins as possible. A common ground is shown in both figures, with the analog and digital ground pins connected to a common plane. Separate power supplies are utilized for the analog and digital sections, with +5V required for the PCM4104 analog supplies and +3.3V required for the digital supply. The +5V analog supply may be derived from a higher valued, positive analog power supply using a linear voltage regulator, such as the REG103 available from Texas Instruments. The +3.3V digital supply can be derived from a primary +5V digital supply using a linear voltage regulator, such as the REG1117, also from TI. The PCM4104EVM evaluation module provides an example of how the common ground with separate supply approach can be successfully implemented. The PCM4104EVM User's Guide includes schematics and PCB layout plots for reference. The evaluation module is available through Texas Instruments' distributors and sales representatives, or may be ordered online through the TI eStore, which can be accessed through the TI home page at http://www.ti.com. The master clock generator supplies the system clock for the PCM4104, as well as the audio data source, such as a digital signal processor. The LRCK and BCK audio clocks should be derived from the system clock, in order to ensure synchronous operation.
ANALOG OUTPUT FILTER CIRCUITS
An external output filter is recommended for each differential output pair. The external output filter further reduces the out-of-band noise energy produced by the delta-sigma modulator, while providing band limiting suitable for audio reproduction. A 2nd-order Butterworth low-pass filter circuit with a -3dB corner frequency from 50kHz to 180kHz is recommended.
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PCM4104
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To Analog Output Filters(1)
(2)
VOUT2+
VREF3+
VREF3-
VOUT3-
VREF2+
VOUT3+ 38
VOUT2-
VCOM1
VREF2-
48 VOUT1+ VOUT1- AGND1 3 VREF1-
(2)
47
46
45
44
43
42
41
40
39
VCOM2 37 VOUT4+ VOUT4- AGND2 34 33 32 VREF4- VREF4+ NC (2)
VCC1
1 2
VCC2
36 35
4 5 6
VREF1+ NC NC
PCM4104
31 NC 30 FS1 29 FS0 28 FMT2 27 FMT1 26 FMT0 25 From Logic, uP, or DSP
7 MODE 8 RST 9 MUTE 10 DEM1 11 DEM0 From Logic, uP, or DSP 12
13 SUB
14 SCKI
15 BCK
16 LRCK
17 DATA0
18 DATA1
19 VDD
20 DGND
21 CS
22 CCLK
23 CDIN
24 CDOUT
+5.0V +3.3V Pin 19 0.1F + Master Clock Generator Pin 40 Audio Data Source 0.1F + Pin 45 10F 0.1F + 10F
10F
(1) Refer to Figure 21 and Figure 22 in this document. (2) Refer to Figure 3 in this document for external connection requirements.
Figure 19. Typical Standalone Mode Configuration
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PCM4104
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To Analog Output Filters(1)
(2)
VOUT2+
VOUT3-
VREF2+
VOUT3+ 38
VOUT2-
VCOM1
VREF3+
VREF2-
VREF3-
48 VOUT1+ VOUT1- AGND1 3 VREF1-
(2)
47
46
45
44
43
42
41
40
39
VCOM2 37 VOUT4+ VOUT4- AGND2 34 33 32 VREF4- VREF4+ NC (2)
VCC1
1 2
VCC2
36 35
4 5 6
VREF1+ NC NC
PCM4104
31 NC 30 FS1 29 FS0 28 FMT2 27 FMT1 26 FMT0 25
7 MODE 8 RST 9 +3.3V MUTE 10 DEM1 11 From Logic or Host Control DEM0 12
13 SUB
14 SCKI
15 BCK
16 LRCK
17 DATA0
18 DATA1
19 VDD
20 DGND
21 CS
22 CCLK
23 CDIN
24 CDOUT
Master Clock Generator +3.3V Pin 19 0.1F +
Audio Data Source
Host Control +5.0V
Pin 40 10F 0.1F
+
Pin 45 10F
0.1F
+
10F
(1) Refer to Figure 21 and Figure 22 in this document. (2) Refer to Figure 3 in this document for external connection requirements.
Figure 20. Typical Software Mode Configuration
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PCM4104
www.ti.com SBAS291B - AUGUST 2003 - REVISED MARCH 2004
1k
560pF +12V 10F + 0.1F PCM4104 100F + 22pF 100F + 604 2200pF 499 2
VOUTn-
7 100 NE5534A 6 Filtered Output RCA or 1/4-inch Phone Jack
604
499
VOUTn+
3 4
0.1F 10F
1k n = 1, 2, 3, or 4
560pF
+
-12V
Figure 21. Single-Ended Output Filter Circuit
1k
560pF
-15V 10F + 0.1F PCM4104 100F + 22pF 100F + 604 2200pF 499 8 EN 604 499 OPA1632 1 VOCM 2 3 10F n = 1, 2, 3, or 4 0.1F + +15V 560pF 4 Filtered Output 5 100 100 2 Male XLR Connector 3 1
6 7
VOUTn+
VOUTn-
1k
Figure 22. Differential Output Filter Circuit
33
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2004
PACKAGING INFORMATION
ORDERABLE DEVICE PCM4104PFBR PCM4104PFBT STATUS(1) ACTIVE ACTIVE PACKAGE TYPE TQFP TQFP PACKAGE DRAWING PFB PFB PINS 48 48 PACKAGE QTY 2000 250
(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
MECHANICAL DATA
MTQF019A - JANUARY 1995 - REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,50 36 25
0,27 0,17
0,08 M
37
24
48
13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0- 7 12
1,20 MAX
0,08 4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

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